1. Field of the Invention
Embodiments of the present invention relate to a non-volatile semiconductor device and a method of fabricating the same. More particularly, embodiments of the present invention relate to a non-volatile memory device having separate charge trap patterns and a method of fabricating the same.
2. Description of the Related Art
Semiconductor memory devices storing data may be classified into volatile memory devices and non-volatile memory devices. While the volatile memory devices lose stored data when a power supply is interrupted, the non-volatile memory devices retain the stored data even when the power supply is interrupted. Accordingly, non-volatile memory devices, e.g., flash memory devices, find wide applications in portable storage devices or mobile telecommunication systems.
Meanwhile, as electronic systems gradually become smaller and require low-power consumption components, the flash memory devices may have to be highly integrated. Therefore, the size of a gate constituting a unit cell of the flash memory device may also have to be scaled down.
Recently, to scale down the size of the gate, a technology of fabricating the flash memory cell by forming a charge trap layer and a control gate on an active region having a fin structure has been developed. Also, a technology employing an insulating layer, e.g., a silicon nitride layer, as the charge trap layer may be considered. NAND-type flash memory devices may be especially amenable to high integration because a number of cells share one contact.
FIG. 1 illustrates a cross-sectional view taken along a word line direction of unit cells of a related art NAND-type flash memory device having a charge trap layer.
Referring to FIG. 1, first and second fins 12A and 12B may be formed on a semiconductor substrate 11 by sinking an isolation trench 13T. An isolation layer 13 may partially fill the isolation trench 13T. The first and second fins 12A and 12B may thus each have a part that projects upward from the isolation layer 13.
A charge trap layer 17 may be applied along a surface of the isolation layer 13, and surfaces of the first and second fins 12A and 12B may project upward from the isolation layer 13. The charge trap layer 17 may be, e.g., a silicon nitride layer. A first tunnel dielectric layer 15A may be between the charge trap layer 17 and the first fin 12A, and a second tunnel dielectric layer 15B may be between the charge trap layer 17 and the second fin 12B.
A control gate electrode 21 may cross over the first and second fins 12A and 12B. The control gate electrode 21 may serve as a word line. A control dielectric layer 19 may be between the control gate electrode 21 and the charge trap layer 17.
Flash memory cells C1 and C2 may be provided at crossing points of the control gate electrode 21 and the fins 12A and 12B, respectively. That is, the first flash memory cell C1 may be provided at the crossing point of the control gate electrode 21 and the first fin 12A, and the second flash memory cell C2 may be provided at the crossing point of the control gate electrode 21 and the second fin 12B.
Electrons may be injected into the charge trap layer 17 by a program operation of the memory cells C1 and C2. The electrons may be injected into the charge trap layer 17 between the first fin 12A and the control gate electrode 21 by the program operation of the first flash memory cell C1. The electrons may also be similarly injected into the charge trap layer 17 between the second fin 12B and the control gate electrode 21 by the program operation of the second flash memory cell C2.
However, the charge trap layers 17 of the first and second flash memory cells C1 and C2 may have a connected structure. The connected structure of the charge trap layers 17 may provide a path for spreading charges. That is, the electrons injected into the charge trap layer 17 may be spread to an adjacent region due to the connected structure of the charge trap layers 17, as indicated by the arrows in FIG. 1. The charge spreading may lead to bad data retention of the memory cells C1 and C2 and malfunction of adjacent memory cells.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.